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Precision Micropower, Low Dropout Voltage References REF19x Series
FEATURES
Initial accuracy: 2 mV maximum Temperature coefficient: 5 ppm/C maximum Low supply current: 45 A maximum Sleep mode: 15 A maximum Low dropout voltage Load regulation: 4 ppm/mA Line regulation: 4 ppm/V High output current: 30 mA Short-circuit protection
TEST PINS
Test Pin 1 and Test Pin 5 are reserved for in-package Zener zap. To achieve the highest level of accuracy at the output, the Zener zapping technique is used to trim the output voltage. Since each unit may require a different amount of adjustment, the resistance value at the test pins varies widely from pin to pin and from part to part. The user should leave Pin 1 and Pin 5 unconnected.
TP 1 VS 2 SLEEP 3
APPLICATIONS
Portable instruments ADCs and DACs Smart sensors Solar-powered applications Loop current-powered instruments
REF19x SERIES
8 7
NC NC
6 OUTPUT TOP VIEW GND 4 (Not to Scale) 5 TP
GENERAL DESCRIPTION
The REF19x series precision band gap voltage references use a patented temperature drift curvature correction circuit and laser trimming of highly stable, thin-film resistors to achieve a very low temperature coefficient and high initial accuracy. The REF19x series is made up of micropower, low dropout voltage (LDV) devices, providing stable output voltage from supplies as low as 100 mV above the output voltage and consuming less than 45 A of supply current. In sleep mode, which is enabled by applying a low TTL or CMOS level to the SLEEP pin, the output is turned off, and supply current is further reduced to less than 15 A. The REF19x series references are specified over the extended industrial temperature range (-40C to +85C), with typical performance specifications over -40C to +125C for applications such as automotive. All electrical grades are available in an 8-lead SOIC_N package; the PDIP and TSSOP packages are available only in the lowest electrical grade. Products are also available in die form.
Figure 1. 8-Lead SOIC_N and TSSOP Pin Configuration (S Suffix and RU Suffix)
TP 1 VS 2 SLEEP 3
6 OUTPUT TOP VIEW GND 4 (Not to Scale) 5 TP
REF19x SERIES
8 7
NC NC
Figure 2. 8-Lead PDIP Pin Configuration (P Suffix)
Table 1. Nominal Output Voltage
Part Number REF191 REF192 REF193 REF194 REF195 REF196 REF198 Nominal Output Voltage (V) 2.048 2.50 3.00 4.50 5.00 3.30 4.096
Rev. I
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
00371-002
NOTES 1. NC = NO CONNECT. 2. TP PINS ARE FACTORY TEST POINTS, NO USER CONNECTION.
00371-001
NOTES 1. NC = NO CONNECT. 2. TP PINS ARE FACTORY TEST POINTS, NO USER CONNECTION.
REF19x Series TABLE OF CONTENTS
Specifications..................................................................................... 3 Electrical Characteristics--REF191 @ TA = 25C .................... 3 Electrical Characteristics--REF191 @ -40C TA +85C .. 4 Electrical Characteristics--REF191 @ -40C TA +125C. 5 Electrical Characteristics--REF192 @ TA = 25C .................... 5 Electrical Characteristics--REF192 @ -40C TA +85C.. 6 Electrical Characteristics--REF192 @ -40C TA +125C 6 Electrical Characteristics--REF193 @ TA = 25C .................... 7 Electrical Characteristics--REF193 @ -40C TA +85C.. 7 Electrical Characteristics--REF193 @ TA -40C +125C 8 Electrical Characteristics--REF194 @ Ta = 25C..................... 8 Electrical Characteristics--REF194 @ -40C TA +85C.. 9 Electrical Characteristics--REF194 @ -40C TA +125C 9 Electrical Characteristics--REF195 @ TA = 25C .................. 10 Electrical Characteristics--REF195 @ -40C TA +85C 10 Electrical Characteristics--REF195 @ -40C TA +125C ....................................................................................................... 11 Electrical Characteristics--REF196 @ TA = 25C .................. 11 Electrical Characteristics--REF196 @ -40C TA +85C 12 Electrical Characteristics--REF196 @ -40C TA +125C ....................................................................................................... 12 Electrical Characteristics--REF198 @ TA = 25C .................. 13 Electrical Characteristics--REF198 @ -40C TA +85C 13 Electrical Characteristics--REF198 @ -40C TA +125C ....................................................................................................... 14 Wafer Test Limits........................................................................ 14 Absolute Maximum Ratings ......................................................... 15 Thermal Resistance .................................................................... 15 ESD Caution................................................................................ 15 Typical Performance Characteristics ........................................... 16 Applications..................................................................................... 19 Output Short-Circuit Behavior ................................................ 19 Device Power Dissipation Considerations.............................. 19 Output Voltage Bypassing ......................................................... 19 Sleep Mode Operation............................................................... 19 Basic Voltage Reference Connections ..................................... 19 Membrane Switch-Controlled Power Supply ......................... 19 Current-Boosted References with Current Limiting............. 20 Negative Precision Reference without Precision Resistors ... 20 Stacking Reference ICs for Arbitrary Outputs ....................... 21 Precision Current Source .......................................................... 21 Switched Output 5 V/3.3 V Reference..................................... 22 Kelvin Connections.................................................................... 22 Fail-Safe 5 V Reference.............................................................. 23 Low Power, Strain Gage Circuit ............................................... 24 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 26
REVISION HISTORY
9/06--Rev. H to Rev. I Updated Format..................................................................Universal Changes to Table 25 ....................................................................... 15 Changes to Figure 6........................................................................ 16 Changes to Figure 10, Figure 12, Figure 14, and Figure 16....... 17 Changes to Figure 18...................................................................... 18 Changes to Figure 20...................................................................... 19 Changes to Figure 23...................................................................... 20 Changes to Figure 25...................................................................... 21 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 26 6/05--Rev. G to Rev. H Updated Format..................................................................Universal Changes to Caption in Figure 7 .................................................... 16 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 26 7/04--Rev. F to Rev. G Changes to Ordering Guide .............................................................4 3/04--Rev. E to Rev. F Updated Absolute Maximum Rating ..............................................4 Changes to Ordering Guide .......................................................... 14 Updated Outline Dimensions....................................................... 24 1/03--Rev. D to Rev. E Changes to Figure 3 and Figure 4................................................. 15 Changes to Output Short Circuit Behavior................................. 17 Changes to Figure 20...................................................................... 17 Changes to Figure 24...................................................................... 19 Updated Outline Dimensions....................................................... 23 1/96--Revision 0: Initial Version
Rev. I | Page 2 of 28
REF19x Series SPECIFICATIONS
ELECTRICAL CHARACTERISTICS--REF191 @ TA = 25C
@ VS = 3.3 V, TA = 25C, unless otherwise noted. Table 2.
Parameter INITIAL ACCURACY 1 E Grade F Grade G Grade LINE REGULATION 2 E Grade F and G Grades LOAD REGULATION2 E Grade F and G Grades DROPOUT VOLTAGE Mnemonic VO Condition IOUT = 0 mA Min 2.046 2.043 2.038 Typ 2.048 Max 2.050 2.053 2.058 4 8 10 15 0.95 1.25 1.55 Unit V V V ppm/V ppm/V ppm/mA ppm/mA V V V mV V p-p
VO/VIN
3.0 V VS 15 V, IOUT = 0 mA
2 4 4 6
VO/VLOAD VS - VO
VS = 5.0 V, 0 mA IOUT 30 mA VS = 3.15 V, ILOAD = 2 mA VS = 3.3 V, ILOAD = 10 mA VS = 3.6 V, ILOAD = 30 mA 1000 hours @ 125C 0.1 Hz to 10 Hz
LONG-TERM STABILITY 3 NOISE VOLTAGE
1 2
DVO eN
1.2 20
Initial accuracy includes temperature hysteresis effect. Line and load regulation specifications include the effect of self-heating. 3 Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.
Rev. I | Page 3 of 28
REF19x Series
ELECTRICAL CHARACTERISTICS--REF191 @ -40C TA +85C
@ VS = 3.3 V, -40C TA +85C, unless otherwise noted. Table 3.
Parameter TEMPERATURE COEFFICIENT 1, 2 E Grade F Grade G Grade 3 LINE REGULATION 4 E Grade F and G Grades LOAD REGULATION4 E Grade F and G Grades DROPOUT VOLTAGE Mnemonic TCVO/C Condition IOUT = 0 mA Min Typ 2 5 10 5 10 5 10 Max 5 10 25 10 20 15 20 0.95 1.25 1.55 Unit ppm/C ppm/C ppm/C ppm/V ppm/V ppm/mA ppm/mA V V V V A V A A A
VO/VIN
3.0 V VS 15 V, IOUT = 0 mA
VO/VLOAD VS - VO
VS = 5.0 V, 0 mA IOUT 25C VS = 3.15 V, ILOAD = 2 mA VS = 3.3 V, ILOAD = 10 mA VS = 3.6 V, ILOAD = 25 mA 2.4
SLEEP PIN Logic High Input Voltage Logic High Input Current Logic Low Input Voltage Logic Low Input Current SUPPLY CURRENT Sleep Mode
1 2
VH IH VL IL No load No load
-8 0.8 -8 45 15
For proper operation, a 1 F capacitor is required between the output pin and the GND pin of the device. TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/C.
TCVO = (VMAX - VMIN)/VO(TMAX - TMIN)
3
Guaranteed by characterization. 4 Line and load regulation specifications include the effect of self-heating.
Rev. I | Page 4 of 28
REF19x Series
ELECTRICAL CHARACTERISTICS--REF191 @ -40C TA +125C
@ VS = 3.3 V, -40C TA +125C, unless otherwise noted. Table 4.
Parameter TEMPERATURE COEFFICIENT 1, 2 E Grade F Grade G Grade 3 LINE REGULATION 4 E Grade F and G Grades LOAD REGULATION4 E Grade F and G Grades DROPOUT VOLTAGE Mnemonic TCVO/C Condition IOUT = 0 mA Min Typ 2 5 10 10 20 10 20 1.25 1.55 Max Unit ppm/C ppm/C ppm/C ppm/V ppm/V ppm/mA ppm/mA V V
VO/VIN
3.0 V VS 15 V, IOUT = 0 mA
VO/VLOAD VS - VO
VS = 5.0 V, 0 mA IOUT 20 mA VS = 3.3 V, ILOAD = 10 mA VS = 3.6 V, ILOAD = 20 mA
1 2
For proper operation, a 1 F capacitor is required between the output pin and the GND pin of the device. TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/C.
TCVO = (VMAX - VMIN)/VO(TMAX - TMIN)
3
Guaranteed by characterization. 4 Line and load regulation specifications include the effect of self-heating.
ELECTRICAL CHARACTERISTICS--REF192 @ TA = 25C
@ VS = 3.3 V, TA = 25C, unless otherwise noted. Table 5.
Parameter INITIAL ACCURACY 1 E Grade F Grade G Grade LINE REGULATION 2 E Grade F and G Grades LOAD REGULATION2 E Grade F and G Grades DROPOUT VOLTAGE LONG-TERM STABILITY 3 NOISE VOLTAGE
1 2 3
Mnemonic VO
Condition IOUT = 0 mA
Min 2.498 2.495 2.490
Typ 2.500
Max 2.502 2.505 2.510 4 8 10 15 1.00 1.40
Unit V V V ppm/V ppm/V ppm/mA ppm/mA V V mV V p-p
VO/VIN
3.0 V VS 15 V, IOUT = 0 mA
2 4 4 6
VO/VLOAD VS - VO DVO eN
VS = 5.0 V, 0 mA IOUT 30 mA VS = 3.5 V, ILOAD = 10 mA VS = 3.9 V, ILOAD = 30 mA 1000 hours @ 125C 0.1 Hz to 10 Hz
1.2 25
Initial accuracy includes temperature hysteresis effect. Line and load regulation specifications include the effect of self-heating. Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.
Rev. I | Page 5 of 28
REF19x Series
ELECTRICAL CHARACTERISTICS--REF192 @ -40C TA +85C
@ VS = 3.3 V, -40C TA +85C, unless otherwise noted. Table 6.
Parameter TEMPERATURE COEFFICIENT 1, 2 E Grade F Grade G Grade 3 LINE REGULATION 4 E Grade F and G Grades LOAD REGULATION4 E Grade F and G Grades DROPOUT VOLTAGE SLEEP PIN Logic High Input Voltage Logic High Input Current Logic Low Input Voltage Logic Low Input Current SUPPLY CURRENT Sleep Mode
1 2
Mnemonic TCVO/C
Condition IOUT = 0 mA
Min
Typ 2 5 10 5 10 5 10
Max 5 10 25 10 20 15 20 1.00 1.50
Unit ppm/C ppm/C ppm/C ppm/V ppm/V ppm/mA ppm/mA V V V A V A A A
VO/VIN
3.0 V VS 15 V, IOUT = 0 mA
VO/VLOAD VS - VO
VS = 5.0 V, 0 mA IOUT 25 mA VS = 3.5 V, ILOAD = 10 mA VS = 4.0 V, ILOAD = 25 mA 2.4
VH IH VL IL No load No load
-8 0.8 -8 45 15
For proper operation, a 1 F capacitor is required between the output pin and the GND pin of the device. TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/C.
TCVO = (VMAX - VMIN)/VO(TMAX - TMIN)
3
Guaranteed by characterization. 4 Line and load regulation specifications include the effect of self-heating.
ELECTRICAL CHARACTERISTICS--REF192 @ -40C TA +125C
@ VS = 3.3 V, -40C TA +125C, unless otherwise noted. Table 7.
Parameter TEMPERATURE COEFFICIENT 1, 2 E Grade F Grade G Grade 3 LINE REGULATION 4 E Grade F and G Grades LOAD REGULATION4 E Grade F and G Grades DROPOUT VOLTAGE Mnemonic TCVO/C Condition IOUT = 0 mA Min Typ 2 5 10 10 20 10 20 1.00 1.50 Max Unit ppm/C ppm/C ppm/C ppm/V ppm/V ppm/mA ppm/mA V V
VO/VIN
3.0 V VS 15 V, IOUT = 0 mA
VO/VLOAD VS - VO
VS = 5.0 V, 0 mA IOUT 20 mA VS = 3.5 V, ILOAD = 10 mA VS = 4.0 V, ILOAD = 20 mA
1 2
For proper operation, a 1 F capacitor is required between the output pin and the GND pin of the device. TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/C.
TCVO = (VMAX - VMIN)/VO(TMAX - TMIN)
3
Guaranteed by characterization. 4 Line and load regulation specifications include the effect of self-heating.
Rev. I | Page 6 of 28
REF19x Series
ELECTRICAL CHARACTERISTICS--REF193 @ TA = 25C
@ VS = 3.3 V, TA = 25C, unless otherwise noted. Table 8.
Parameter INITIAL ACCURACY 1 G Grade LINE REGULATION 2 G Grade LOAD REGULATION2 G Grade DROPOUT VOLTAGE LONG-TERM STABILITY 3 NOISE VOLTAGE
1 2 3
Mnemonic VO VO/VIN VO/VLOAD VS - VO DVO eN
Condition IOUT = 0 mA 3.3 V, VS 15 V, IOUT = 0 mA VS = 5.0 V, 0 mA IOUT 30 mA VS = 3.8 V, ILOAD = 10 mA VS = 4.0 V, ILOAD = 30 mA 1000 hours @ 125C 0.1 Hz to 10 Hz
Min 2.990
Typ 3.0 4 6
Max 3.010 8 15 0.80 1.00
Unit V ppm/V ppm/mA V V mV V p-p
1.2 30
Initial accuracy includes temperature hysteresis effect. Line and load regulation specifications include the effect of self-heating. Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.
ELECTRICAL CHARACTERISTICS--REF193 @ -40C TA +85C
@ VS = 3.3 V, -40C TA +85C, unless otherwise noted. Table 9.
Parameter TEMPERATURE COEFFICIENT 1, 2 G Grade 3 LINE REGULATION 4 G Grade LOAD REGULATION4 G Grade DROPOUT VOLTAGE SLEEP PIN Logic High Input Voltage Logic High Input Current Logic Low Input Voltage Logic Low Input Current SUPPLY CURRENT Sleep Mode
1 2
Mnemonic TCVO/C VO/VIN VO/VLOAD VS - VO
Condition IOUT = 0 mA 3.3 V VS 15 V, IOUT = 0 mA VS = 5.0 V, 0 mA IOUT 25 mA VS = 3.8 V, ILOAD = 10 mA VS = 4.1 V, ILOAD = 30 mA
Min
Typ 10 10 10
Max 25 20 20 0.80 1.10
Unit ppm/C ppm/V ppm/mA V V V A V A A A
VH IH VL IL No load No load
2.4 -8 0.8 -8 45 15
For proper operation, a 1 F capacitor is required between the output pin and the GND pin of the device. TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/C.
TCVO = (VMAX - VMIN)/VO(TMAX - TMIN)
3 4
Guaranteed by characterization. Line and load regulation specifications include the effect of self-heating.
Rev. I | Page 7 of 28
REF19x Series
ELECTRICAL CHARACTERISTICS--REF193 @ TA -40C +125C
@ VS = 3.3 V, -40C TA +125C, unless otherwise noted. Table 10.
Parameter TEMPERATURE COEFFICIENT 1 ,2 G Grade 3 LINE REGULATION 4 G Grade LOAD REGULATION4 G Grade DROPOUT VOLTAGE Mnemonic TCVO/C VO/VIN VO/VLOAD VS - VO Condition IOUT = 0 mA 3.3 V VS 15 V, IOUT = 0 mA VS = 5.0 V, 0 mA IOUT 20 mA VS = 3.8 V, ILOAD = 10 mA VS = 4.1 V, ILOAD = 20 mA Min Typ 10 20 10 0.80 1.10 Max Unit ppm/C ppm/V ppm/mA V V
1 2
For proper operation, a 1 F capacitor is required between the output pin and the GND pin of the device. TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/C.
TCVO = (VMAX - VMIN)/VO(TMAX - TMIN)
3
Guaranteed by characterization. 4 Line and load regulation specifications include the effect of self-heating.
ELECTRICAL CHARACTERISTICS--REF194 @ TA = 25C
@ VS = 5.0 V, TA = 25C, unless otherwise noted. Table 11.
Parameter INITIAL ACCURACY 1 E Grade F Grade G Grade LINE REGULATION 2 E Grade F and G Grades LOAD REGULATION2 E Grade F and G Grades DROPOUT VOLTAGE LONG-TERM STABILITY 3 NOISE VOLTAGE
1 2
Mnemonic VO
Condition IOUT = 0 mA
Min 4.498 4.495 4.490
Typ 4.5
Max 4.502 4.505 4.510 4 8 4 8 0.50 1.30
Unit V V V ppm/V ppm/V ppm/mA ppm/mA V V mV V p-p
VO/VIN
4.75 V VS 15 V, IOUT = 0 mA
2 4 2 4
VO/VLOAD VS - VO DVO eN
VS = 5.8 V, 0 mA IOUT 30 mA VS = 5.00 V, ILOAD = 10 mA VS = 5.8 V, ILOAD = 30 mA 1000 hours @ 125C 0.1 Hz to 10 Hz
2 45
Initial accuracy includes temperature hysteresis effect. Line and load regulation specifications include the effect of self-heating. 3 Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.
Rev. I | Page 8 of 28
REF19x Series
ELECTRICAL CHARACTERISTICS--REF194 @ -40C TA +85C
@ VS = 5.0 V, -40C TA +85C, unless otherwise noted. Table 12.
Parameter TEMPERATURE COEFFICIENT 1, 2 E Grade F Grade G Grade 3 LINE REGULATION 4 E Grade F and G Grades LOAD REGULATION4 E Grade F and G Grades DROPOUT VOLTAGE SLEEP PIN Logic High Input Voltage Logic High Input Current Logic Low Input Voltage Logic Low Input Current SUPPLY CURRENT Sleep Mode
1 2
Mnemonic TCVO/C
Condition IOUT = 0 mA
Min
Typ 2 5 10 5 10 5 10
Max 5 10 25 10 20 15 20 0.5 1.30
Unit ppm/C ppm/C ppm/C ppm/V ppm/V ppm/mA ppm/mA V V V A V A A A
VO/VIN
4.75 V VS 15 V, IOUT = 0 mA
VO/VLOAD VS - VO
VS = 5.80 V, 0 mA IOUT 25 mA VS = 5.00 V, ILOAD = 10 mA VS = 5.80 V, ILOAD = 25 mA 2.4
VH IH VL IL No load No load
-8 0.8 -8 45 15
For proper operation, a 1 F capacitor is required between the output pin and the GND pin of the device. TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/C.
TCVO = (VMAX - VMIN)/VO(TMAX - TMIN)
3
Guaranteed by characterization. 4 Line and load regulation specifications include the effect of self-heating.
ELECTRICAL CHARACTERISTICS--REF194 @ -40C TA +125C
@ VS = 5.0 V, -40C TA +125C, unless otherwise noted. Table 13.
Parameter TEMPERATURE COEFFICIENT 1, 2 E Grade F Grade G Grade 3 LINE REGULATION 4 E Grade F and G Grades LOAD REGULATION E Grade F and G Grades DROPOUT VOLTAGE Mnemonic TCVO/C Condition IOUT = 0 mA Min Typ 2 5 10 5 10 5 10 0.60 1.45 Max Unit ppm/C ppm/C ppm/C ppm/V ppm/V ppm/mA ppm/mA V V
VO/VIN
4.75 V VS 15 V, IOUT = 0 mA
VO/VLOAD VS - VO
VS = 5.80 V, 0 mA IOUT 20 mA VS = 5.10 V, ILOAD = 10 mA VS = 5.95 V, ILOAD = 20 mA
1 2
For proper operation, a 1 F capacitor is required between the output pin and the GND pin of the device. TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/C.
TCVO = (VMAX - VMIN)/VO(TMAX - TMIN)
3 4
Guaranteed by characterization. Line and load regulation specifications include the effect of self-heating.
Rev. I | Page 9 of 28
REF19x Series
ELECTRICAL CHARACTERISTICS--REF195 @ TA = 25C
@ VS = 5.10 V, TA = 25C, unless otherwise noted. Table 14.
Parameter INITIAL ACCURACY 1 E Grade F Grade G Grade LINE REGULATION 2 E Grade F and G Grades LOAD REGULATION2 E Grade F and G Grades DROPOUT VOLTAGE LONG-TERM STABILITY 3 NOISE VOLTAGE
1 2 3
Mnemonic VO
Condition IOUT = 0 mA
Min 4.998 4.995 4.990
Typ 5.0
Max 5.002 5.005 5.010 4 8 4 8 0.50 1.30
Unit V V V ppm/V ppm/V ppm/mA ppm/mA V V mV V p-p
VO/VIN
5.10 V VS 15 V, IOUT = 0 mA
2 4 2 4
VO/VLOAD VS - VO DVO eN
VS = 6.30 V, 0 mA IOUT 30 mA VS = 5.50 V, ILOAD = 10 mA VS = 6.30 V, ILOAD = 30 mA 1000 hours @ 125C 0.1 Hz to 10 Hz
1.2 50
Initial accuracy includes temperature hysteresis effect. Line and load regulation specifications include the effect of self-heating. Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.
ELECTRICAL CHARACTERISTICS--REF195 @ -40C TA +85C
@ VS = 5.15 V, -40C TA +85C, unless otherwise noted. Table 15.
Parameter TEMPERATURE COEFFICIENT 1,2 E Grade F Grade G Grade 3 LINE REGULATION 4 E Grade F and G Grades LOAD REGULATION4 E Grade F and G Grades DROPOUT VOLTAGE SLEEP PIN Logic High Input Voltage Logic High Input Current Logic Low Input Voltage Logic Low Input Current SUPPLY CURRENT Sleep Mode
1 2
Mnemonic TCVO/C
Condition IOUT = 0 mA
Min
Typ 2 5 10 5 10 5 10
Max 5 10 25 10 20 10 20 0.50 1.30
Unit ppm/C ppm/C ppm/C ppm/V ppm/V ppm/mA ppm/mA V V V A V A A A
VO/VIN
5.15 V VS 15 V, IOUT = 0 mA
VO/VLOAD VS - VO
VS = 6.30 V, 0 mA IOUT 25 mA VS = 5.50 V, ILOAD = 10 mA VS = 6.30 V, ILOAD = 25 mA 2.4
VH IH VL IL No load No load
-8 0.8 -8 45 15
For proper operation, a 1 F capacitor is required between the output pin and the GND pin of the device. TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/C.
TCVO = (VMAX - VMIN)/VO(TMAX - TMIN)
3 4
Guaranteed by characterization. Line and load regulation specifications include the effect of self-heating.
Rev. I | Page 10 of 28
REF19x Series
ELECTRICAL CHARACTERISTICS--REF195 @ -40C TA +125C
@ VS = 5.20 V, -40C TA +125C, unless otherwise noted. Table 16.
Parameter TEMPERATURE COEFFICIENT 1, 2 E Grade F Grade G Grade 3 LINE REGULATION 4 E Grade F and G Grades LOAD REGULATION4 E Grade F and G Grades DROPOUT VOLTAGE Mnemonic TCVO/C Condition IOUT = 0 mA Min Typ 2 5 10 5 10 5 10 0.60 1.45 Max Unit ppm/C ppm/C ppm/C ppm/V ppm/V ppm/mA ppm/mA V V
VO/VIN
5.20 V VS 15 V, IOUT = 0 mA
VO/VLOAD VS - VO
VS = 6.45 V, 0 mA IOUT 20 mA VS = 5.60 V, ILOAD = 10 mA VS = 6.45 V, ILOAD = 20 mA
1 2
For proper operation, a 1 F capacitor is required between the output pin and the GND pin of the device. TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/C.
TCVO = (VMAX - VMIN)/VO(TMAX - TMIN)
3
Guaranteed by characterization. 4 Line and load regulation specifications include the effect of self-heating.
ELECTRICAL CHARACTERISTICS--REF196 @ TA = 25C
@ VS = 3.5 V, TA = 25C, unless otherwise noted. Table 17.
Parameter INITIAL ACCURACY 1 G Grade LINE REGULATION 2 G Grade LOAD REGULATION2 G Grade DROPOUT VOLTAGE LONG-TERM STABILITY 3 NOISE VOLTAGE
1 2
Mnemonic VO VO/VIN VO/VLOAD VS - VO DVO eN
Condition IOUT = 0 mA 3.50 V VS 15 V, IOUT = 0 mA VS = 5.0 V, 0 mA IOUT 30 mA VS = 4.1 V, ILOAD = 10 mA VS = 4.3 V, ILOAD = 30 mA 1000 hours @ 125C 0.1 Hz to 10 Hz
Min 3.290
Typ 3.3 4 6
Max 3.310 8 15 0.80 1.00
Unit V ppm/V ppm/mA V V mV V p-p
1.2 33
Initial accuracy includes temperature hysteresis effect. Line and load regulation specifications include the effect of self-heating. 3 Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.
Rev. I | Page 11 of 28
REF19x Series
ELECTRICAL CHARACTERISTICS--REF196 @ -40C TA +85C
@ VS = 3.5 V, -40C TA +85C, unless otherwise noted. Table 18.
Parameter TEMPERATURE COEFFICIENT 1, 2 G Grade 3 LINE REGULATION 4 G Grade LOAD REGULATION4 G Grade DROPOUT VOLTAGE SLEEP PIN Logic High Input Voltage Logic High Input Current Logic Low Input Voltage Logic Low Input Current SUPPLY CURRENT Sleep Mode
1 2
Mnemonic TCVO/C VO/VIN VO/VLOAD VS - VO
Condition IOUT = 0 mA 3.5 V VS 15 V, IOUT = 0 mA VS = 5.0 V, 0 mA IOUT 25 mA VS = 4.1 V, ILOAD = 10 mA VS = 4.3 V, ILOAD = 25 mA
Min
Typ 10 10 10
Max 25 20 20 0.80 1.00
Unit ppm/C ppm/V ppm/mA V V V A V A A A
VH IH VL IL No load No load
2.4 -8 0.8 -8 45 15
For proper operation, a 1 F capacitor is required between the output pin and the GND pin of the device. TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/C.
TCVO = (VMAX - VMIN)/VO(TMAX - TMIN)
3
Guaranteed by characterization. 4 Line and load regulation specifications include the effect of self-heating.
ELECTRICAL CHARACTERISTICS--REF196 @ -40C TA +125C
@ VS = 3.50 V, -40C TA +125C, unless otherwise noted. Table 19.
Parameter TEMPERATURE COEFFICIENT 1, 2 G Grade 3 LINE REGULATION 4 G Grade LOAD REGULATION4 G Grade DROPOUT VOLTAGE Mnemonic TCVO/C VO/VIN VO/VLOAD VS - VO Condition IOUT = 0 mA 3.50 V VS 15 V, IOUT = 0 mA VS = 5.0 V, 0 mA IOUT 20 mA VS = 4.1 V, ILOAD = 10 mA VS = 4.4 V, ILOAD = 20 mA Min Typ 10 20 20 0.80 1.10 Max Unit ppm/C ppm/V ppm/mA V V
1 2
For proper operation, a 1 F capacitor is required between the output pin and the GND pin of the device. TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/C.
TCVO = (VMAX - VMIN)/VO(TMAX - TMIN)
3
Guaranteed by characterization. 4 Line and load regulation specifications include the effect of self-heating.
Rev. I | Page 12 of 28
REF19x Series
ELECTRICAL CHARACTERISTICS--REF198 @ TA = 25C
@ VS = 5.0 V, TA = 25C, unless otherwise noted. Table 20.
Parameter INITIAL ACCURACY 1 E Grade F Grade G Grade LINE REGULATION 2 E Grade F and G Grades LOAD REGULATION2 E Grade F and G Grades DROPOUT VOLTAGE LONG-TERM STABILITY 3 NOISE VOLTAGE
1 2 3
Mnemonic VO
Condition IOUT = 0 mA
Min 4.094 4.091 4.086
Typ 4.096
Max 4.098 4.101 4.106 4 8 4 8 0.502 1.30
Unit V V V ppm/V ppm/V ppm/mA ppm/mA V V mV V p-p
VO/VIN
4.5 V VS 15 V, IOUT = 0 mA
2 4 2 4
VO/VLOAD VS - VO DVO eN
VS = 5.4 V, 0 mA IOUT 30 mA VS = 4.6 V, ILOAD = 10 mA VS = 5.4 V, ILOAD = 30 mA 1000 hours @ 125C 0.1 Hz to 10 Hz
1.2 40
Initial accuracy includes temperature hysteresis effect. Line and load regulation specifications include the effect of self-heating. Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.
ELECTRICAL CHARACTERISTICS--REF198 @ -40C TA +85C
@ VS = 5.0 V, -40C TA +85C, unless otherwise noted. Table 21.
Parameter TEMPERATURE COEFFICIENT 1, 2 E Grade F Grade G Grade 3 LINE REGULATION 4 E Grade F and G Grades LOAD REGULATION4 E Grade F and G Grades DROPOUT VOLTAGE SLEEP PIN Logic High Input Voltage Logic High Input Current Logic Low Input Voltage Logic Low Input Current SUPPLY CURRENT Sleep Mode
1 2
Mnemonic TCVO/C
Condition IOUT = 0 mA
Min
Typ 2 5 10 5 10 5 10
Max 5 10 25 10 20 10 20 0.502 1.30
Unit ppm/C ppm/C ppm/C ppm/V ppm/V ppm/mA ppm/mA V V V A V A A A
VO/VIN
4.5 V VS 15 V, IOUT = 0 mA
VO/VLOAD VS - VO
VS = 5.4 V, 0 mA IOUT 25 mA VS = 4.6 V, ILOAD = 10 mA VS = 5.4 V, ILOAD = 25 mA 2.4
VH IH VL IL No load No load
-8 0.8 -8 45 15
For proper operation, a 1 F capacitor is required between the output pin and the GND pin of the device. TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/C.
TCVO = (VMAX - VMIN)/VO(TMAX - TMIN)
3
Guaranteed by characterization. 4 Line and load regulation specifications include the effect of self-heating.
Rev. I | Page 13 of 28
REF19x Series
ELECTRICAL CHARACTERISTICS--REF198 @ -40C TA +125C
@ VS = 5.0 V, -40C TA +125C, unless otherwise noted. Table 22.
Parameter TEMPERATURE COEFFICIENT 1, 2 E Grade F Grade G Grade 3 LINE REGULATION 4 E Grade F and G Grades LOAD REGULATION4 E Grade F and G Grades DROPOUT VOLTAGE Mnemonic TCVO/C Condition IOUT = 0 mA Min Typ 2 5 10 5 10 5 10 0.60 1.50 Max Unit ppm/C ppm/C ppm/C ppm/V ppm/V ppm/mA ppm/mA V V
VO/VIN
4.5 V VS 15 V, IOUT = 0 mA
VO/VLOAD VS - VO
VS = 5.6 V, 0 mA IOUT 20 mA VS = 4.7 V, ILOAD = 10 mA VS = 5.6 V, ILOAD = 20 mA
1 2
For proper operation, a 1 F capacitor is required between the output pin and the GND pin of the device. TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/C.
TCVO = (VMAX - VMIN)/VO(TMAX - TMIN)
3 4
Guaranteed by characterization. Line and load regulation specifications include the effect of self-heating.
WAFER TEST LIMITS
For proper operation, a 1 F capacitor is required between the output pins and the GND pin of the REF19x. Electrical tests and wafer probe to the limits are shown in Table 23. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. @ ILOAD = 0 mA, TA = 25C, unless otherwise noted. Table 23.
Parameter INITIAL ACCURACY REF191 REF192 REF193 REF194 REF195 REF196 REF198 LINE REGULATION LOAD REGULATION DROPOUT VOLTAGE SLEEP MODE INPUT Logic Input High Logic Input Low SUPPLY CURRENT Sleep Mode Mnemonic VO Condition Limit 2.043/2.053 2.495/2.505 2.990/3.010 4.495/4.505 4.995/5.005 3.290/3.310 4.091/4.101 15 15 1.25 1.55 2.4 0.8 45 15 Unit V V V V V V V ppm/V ppm/mA V V V V A A
VO/VIN VO/ILOAD VO - V+
(VO + 0.5 V) < VIN < 15 V, IOUT = 0 mA 0 mA < ILOAD < 30 mA, VIN = (VO + 1.3 V) ILOAD = 10 mA ILOAD = 30 mA
VIH VIL VIN = 15 V
No load No load
Rev. I | Page 14 of 28
REF19x Series ABSOLUTE MAXIMUM RATINGS
Table 24.
Parameter 1 Supply Voltage Output to GND Output to GND Short-Circuit Duration Storage Temperature Range PDIP, SOIC_N Package Operating Temperature Range REF19x Junction Temperature Range PDIP, SOIC_N Package Lead Temperature Range (Soldering 60 sec)
1
Rating -0.3 V, +18 V -0.3 V, VS + 0.3 V Indefinite -65C to +150C -40C to +85C -65C to +150C 300C
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 25. Thermal Resistance
Package Type 8-Lead PDIP 8-Lead SOIC_N
1
JA 1 103 158
JC 43 43
Unit C/W C/W
JA is specified for worst-case conditions; that is, JA is specified for the device in socket for PDIP and is specified for the device soldered in the circuit board for the SOIC package.
Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. I | Page 15 of 28
REF19x Series TYPICAL PERFORMANCE CHARACTERISTICS
5.004 5.003 5.002 PERCENTAGE OF PARTS
00371-003
3 TYPICAL PARTS 5.15V < VIN < 15V
50 BASED ON 600 45 UNITS, 4 RUNS -40C TA +85C 40 35 30 25 20 15 10 5
OUTPUT VOLTAGE (V)
5.001 5.000 4.999 4.998 4.997 4.996 -50
-25
0 25 50 TEMPERATURE (C)
75
100
15
10
5 0 5 TC--VOUT (ppm/C)
10
15
20
Figure 3. REF195 Output Voltage vs. Temperature
32 28
Figure 6. TC--VOUT Distribution
40 35 NORMAL MODE 30
5.15V VS 15V
LOAD REGULATION (ppm/V)
24 20 16 +25C 12 8 4 0 +85C -40C
SUPPLY CURRENT (A)
25 20 15 10 5 SLEEP MODE
00371-007 00371-008
00371-004
0
5
10
15 ILOAD (mA)
20
25
30
0 -50
-25
0 25 50 TEMPERATURE (C)
75
100
Figure 4. REF195 Load Regulator vs. ILOAD
20
Figure 7. Supply Current vs. Temperature
-6
0mA IOUT 25mA +85C
16
-5 SLEEP PIN CURRENT (A)
LINE REGULATION (ppm/mA)
+25C 12 -40C 8
-4
-3
-2 VL -1 VH
4
00371-005
0
4
6
8
10 VIN (V)
12
14
16
0 -50
-25
0 25 50 TEMPERATURE (C)
75
100
Figure 5. REF195 Line Regulator vs. VIN
Figure 8. SLEEP Pin Current vs. Temperature
Rev. I | Page 16 of 28
00371-006
0 20
REF19x Series
REF19x
0 -20
RIPPLE REJECTION (dB)
VIN = 15V
2 6 4
1F 0
-40 -60 -80 -100 -120
00371-009
Figure 13. Load Transient Response Measurement Circuit
2V
100% 90%
10
100
1k 10k FREQUENCY (Hz)
100k
1M
Figure 9. Ripple Rejection vs. Frequency
10F
1mA LOAD
10%
30mA LOAD
REF
Figure 10. Ripple Rejection vs. Frequency Measurement Circuit
00371-010
10F
4
1F
1k
2V
100s
Figure 14. Power-On Response Time
VIN = 7V
REF19x
2 4 6
200V VG = 2V p-p 1F Z VS = 4V
2
REF19x
6
1F
1F
Figure 15. Power-On Response Time Measurement Circuit
ZO () 4 3 2 1 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M
00371-011
5V ON 100% OFF
90%
0
Figure 11. Output Impedance vs. Frequency
VOUT IL = 10mA
IL = 1mA
5V OFF 100% ON 90%
10% 0%
00371-016
1V
2ms
Figure 16. SLEEP Response Time
VIN = 15V
REF19x
2 6 3 4
VOUT
00371-017
10% 0% 20mV 100s
00371-012
1F
Figure 12. Load Transient Response
Figure 17. SLEEP Response Time Measurement Circuit
Rev. I | Page 17 of 28
00371-015
VIN = 7V
4
00371-014
VIN = 15V
1k
REF19x
2 6
10F OUTPUT
0%
00371-013
10mA
REF19x Series
35 5V
100% 90%
30 25 20 15 10 5 200mV 200s
00371-018
10% 0%
LOAD CURRENT (mA)
0
0.1
0.2 0.3 0.4 0.5 0.6 0.7 REF195 DROPOUT VOLTAGE (V)
0.8
0.9
Figure 18. Line Transient Response
Figure 19. Load Current vs. Dropout Voltage
Rev. I | Page 18 of 28
00371-019
0
REF19x Series APPLICATIONS
OUTPUT SHORT-CIRCUIT BEHAVIOR
The REF19x family of devices is completely protected from damage due to accidental output shorts to GND or to V+. In the event of an accidental short-circuit condition, the reference device shuts down and limits its supply current to 40 mA.
V+
SLEEP MODE OPERATION
All REF19x devices include a sleep capability that is TTL/CMOS-level compatible. Internally, a pull-up current source to VIN is connected at the SLEEP pin. This permits the SLEEP pin to be driven from an open collector/drain driver. A logic low or a 0 V condition on the SLEEP pin is required to turn off the output stage. During sleep, the output of the references becomes a high impedance state where its potential would then be determined by external circuitry. If the sleep feature is not used, it is recommended that the SLEEP pin be connected to VIN (Pin 2).
VOUT
SLEEP (SHUTDOWN)
BASIC VOLTAGE REFERENCE CONNECTIONS
The circuit in Figure 21 illustrates the basic configuration for the REF19x family of references. Note the 10 F/0.1 F bypass network on the input and the 1 F/0.1 F bypass network on the output. It is recommended that no connections be made to Pin 1, Pin 5, Pin 7, and Pin 8. If the sleep feature is not required, Pin 3 should be connected to VIN.
REF19x
NC 1 VIN
2 8 7 6 5
GND
Figure 20. Simplified Schematic
DEVICE POWER DISSIPATION CONSIDERATIONS
The REF19x family of references is capable of delivering load currents to 30 mA with an input voltage that ranges from 3.3 V to 5 V. When these devices are used in applications with large input voltages, exercise care to avoid exceeding the maximum internal power dissipation of these devices. Exceeding the published specifications for maximum power dissipation or junction temperature can result in premature device failure. The following formula should be used to calculate a device's maximum junction temperature or dissipation:
00371-020
NC NC OUTPUT
00371-021
10F
0.1F
SLEEP 3
4
NC
+ 1F TANT
0.1F
NC = NO CONNECT
Figure 21. Basic Voltage Reference Configuration
MEMBRANE SWITCH-CONTROLLED POWER SUPPLY
With output load currents in the tens of mA, the REF19x family of references can operate as a low dropout power supply in hand-held instrument applications. In the circuit shown in Figure 22, a membrane on/off switch is used to control the operation of the reference. During an initial power-on condition, the SLEEP pin is held to GND by the 10 k resistor. Recall that this condition (read: three-state) disables the REF19x output. When the membrane on switch is pressed, the SLEEP pin is momentarily pulled to VIN, enabling the REF19x output. At this point, current through the 10 k resistor is reduced, and the internal current source connected to the SLEEP pin takes control. Pin 3 assumes and remains at the same potential as VIN. When the membrane off switch is pressed, the SLEEP pin is momentarily connected to GND, which once again disables the REF19x output.
PD =
TJ - TA JA
In this equation, TJ and TA are the junction and ambient temperatures, respectively; PD is the device power dissipation; and JA is the device package thermal resistance.
OUTPUT VOLTAGE BYPASSING
For stable operation, low dropout voltage regulators and references generally require a bypass capacitor connected from their VOUT pins to their GND pins. Although the REF19x family of references is capable of stable operation with capacitive loads exceeding 100 F, a 1 F capacitor is sufficient to guarantee rated performance. The addition of a 0.1 F ceramic capacitor in parallel with the bypass capacitor improves load current transient performance. For best line voltage transient performance, it is recommended that the voltage inputs of these devices be bypassed with a 10 F electrolytic capacitor in parallel with a 0.1 F ceramic capacitor.
Rev. I | Page 19 of 28
REF19x Series
REF19x
NC 1 VIN 1k 5% ON
2 3 4 8 7 6 5
NC NC OUTPUT NC +1F TANT
10k OFF NC = NO CONNECT
00371-022
The requirement for a heat sink on Q1 depends on the maximum input voltage and short-circuit current. With VS = 5 V and a 300 mA current limit, the worst-case dissipation of Q1 is 1.5 W, less than the TO-220 package 2 W limit. However, if smaller TO-39 or TO-5 packaged devices, such as the 2N4033, are used, the current limit should be reduced to keep maximum dissipation below the package rating. This is accomplished by simply raising R4. A tantalum output capacitor is used at C1 for its low equivalent series resistance (ESR), and the higher value is required for stability. Capacitor C2 provides input bypassing and can be an ordinary electrolytic. Shutdown control of the booster stage is an option, and when used, some cautions are needed. Due to the additional active devices in the VS line to U1, a direct drive to Pin 3 does not work as with an unbuffered REF19x device. To enable shutdown control, the connection from U1 to U2 is broken at the X, and Diode D1 then allows a CMOS control source, VC, to drive U1 to U3 for on/off operation. Startup from shutdown is not as clean under heavy load as it is in basic REF19x series, and can require several milliseconds under load. Nevertheless, it is still effective and can fully control 150 mA loads. When shutdown control is used, heavy capacitive loads should be minimized.
Figure 22. Membrane Switch-Controlled Power Supply
CURRENT-BOOSTED REFERENCES WITH CURRENT LIMITING
While the 30 mA rated output current of the REF19x series is higher than is typical of other reference ICs, it can be boosted to higher levels, if desired, with the addition of a simple external PNP transistor, as shown in Figure 23. Full-time current limiting is used to protect the pass transistor against shorts.
+VS = 6V TO 9V (SEE TEXT) Q2 2N3906 +
2
R4 2 R1 1k
Q1 TIP32A (SEE TEXT)
OUTPUT TABLE U1 REF192 REF193 REF196 REF194 REF195 VOUT (V) 2.5 3.0 3.3 4.5 5.0
C2 100F 25V
R2 1.5k C3 0.1F
6
D1 VC
3
1N4148 (SEE TEXT ON SLEEP)
(SEE TABLE) 4
REF196
U1
F S +VOUT 3.3V @ 150mA + R1 VOUT COMMON
C1 10F/25V R3 1.82k (TANTALUM) S F
NEGATIVE PRECISION REFERENCE WITHOUT PRECISION RESISTORS
In many current-output CMOS DAC applications where the output signal voltage must be the same polarity as the reference voltage, it is often necessary to reconfigure a current-switching DAC into a voltage-switching DAC using a 1.25 V reference, an op amp, and a pair of resistors. Using a current-switching DAC directly requires an additional operational amplifier at the output to reinvert the signal. A negative voltage reference is then desirable, because an additional operational amplifier is not required for either reinversion (current-switching mode) or amplification (voltage-switching mode) of the DAC output voltage. In general, any positive voltage reference can be converted into a negative voltage reference using an operational amplifier and a pair of matched resistors in an inverting configuration. The disadvantage to this approach is that the largest single source of error in the circuit is the relative matching of the resistors used. The circuit illustrated in Figure 24 avoids the need for tightly matched resistors by using an active integrator circuit. In this circuit, the output of the voltage reference provides the input drive for the integrator. To maintain circuit equilibrium, the integrator adjusts its output to establish the proper relationship between the reference's VOUT and GND. Thus, any desired negative output voltage can be selected by substituting for the appropriate reference IC. The sleep feature is maintained in the circuit with the simple addition of a PNP transistor and a 10 k resistor.
VS COMMON
Figure 23. Boosted 3.3 V Referenced with Current Limiting
In this circuit, the power supply current of reference U1 flowing through R1 to R2 develops a base drive for Q1, whose collector provides the bulk of the output current. With a typical gain of 100 in Q1 for 100 mA to 200 mA loads, U1 is never required to furnish more than a few mA, so this factor minimizes temperature-related drift. Short-circuit protection is provided by Q2, which clamps the drive to Q1 at about 300 mA of load current, with values as shown in Figure 23. With this separation of control and power functions, dc stability is optimum, allowing most advantageous use of premium grade REF19x devices for U1. Of course, load management should still be exercised. A short, heavy, low dc resistance (DCR) conductor should be used from U1 to U6 to the VOUT Sense Point S, where the collector of Q1 connects to the load, Point F. Because of the current limiting configuration, the dropout voltage circuit is raised about 1.1 V over that of the REF19x devices, due to the VBE of Q1 and the drop across Current Sense Resistor R4. However, overall dropout is typically still low enough to allow operation of a 5 V to 3.3 V regulator/reference using the REF196 for U1 as noted, with a VS as low as 4.5 V and a load current of 150 mA.
Rev. I | Page 20 of 28
00371-023
REF19x Series
One caveat to this approach is that although rail-to-rail output amplifiers work best in the application, these operational amplifiers require a finite amount (mV) of headroom when required to provide any load current. The choice for the circuit's negative supply should take this issue into account.
VIN 10k SLEEP TTL/CMOS 2N3906
2
VIN
3
SLEEP VOUT 6
1k +5V 1F
1F
REF19x
GND
4
A1
-5V
100
-VREF
While this concept is simple, some cautions are needed. Since the lower reference circuit must sink a small bias current from U2 (50 A to 100 A), plus the base current from the series PNP output transistor in U2, either the external load of U1 or R1 must provide a path for this current. If the U1 minimum load is not well defined, Resistor R1 should be used, set to a value that conservatively passes 600 A of current with the applicable VOUT1 across it. Note that the two U1 and U2 reference circuits are locally treated as macrocells, each having its own bypasses at input and output for best stability. Both U1 and U2 in this circuit can source dc currents up to their full rating. The minimum input voltage, VS, is determined by the sum of the outputs, VOUT2, plus the dropout voltage of U2. A related variation on stacking two 3-terminal references is shown in Figure 26, where U1, a REF192, is stacked with a 2-terminal reference diode, such as the AD589. Like the 3-terminal stacked reference above, this circuit provides two outputs, VOUT1 and VOUT2, which are the individual terminal voltages of D1 and U1, respectively. Here this is 1.235 V and 2.5 V, which provides a VOUT2 of 3.735 V. When using 2-terminal reference diodes, such as D1, the rated minimum and maximum device currents must be observed, and the maximum load current from VOUT1 can be no greater than the current setup by R1 and VO (U1). When VO (U1) is equal to 2.5 V, R1 provides a 500 A bias to D1, so the maximum load current available at VOUT1 is 450 A or less.
+VS VS > VOUT2 + 0.15V
10k
100k
00371-024
A1 = 1/2 OP295, 1/2 OP291
Figure 24. Negative Precision Voltage Reference Uses No Precision Resistors
STACKING REFERENCE ICS FOR ARBITRARY OUTPUTS
Some applications may require two reference voltage sources that are a combined sum of standard outputs. The circuit shown in Figure 25 shows how this stacked output reference can be implemented.
OUTPUT TABLE U1/U2 +VS VS > VOUT2 + 0.15V
2
VOUT1 (V) VOUT2 (V) 5.0 7.0 7.5
REF192/REF192 2.5 REF192/REF194 2.5 REF192/REF195 2.5 U2
C1 0.1F
3
(SEE TABLE) 4
REF19x
6
+VOUT2 VO (U2) + C2 1F
2
C1 0.1F
3
REF192
4
U1
6
VO (U1)
+
C2 1F
R1 4.99k
(SEE TEXT)
+VOUT2 3.735V
2
C3 0.1F VIN COMMON
3
(SEE TABLE) 4
REF19x
U1
6
(SEE TEXT)
VOUT COMMON
00371-025
VOUT COMMON
Figure 26. Stacking Voltage References with the REF192
Figure 25. Stacking Voltage References with the REF19x
PRECISION CURRENT SOURCE
In low power applications, the need often arises for a precision current source that can operate on low supply voltages. As shown in Figure 27, any one of the devices in the REF19x family of references can be configured as a precision current source. The circuit configuration illustrated is a floating current source with a grounded load. The output voltage of the reference is bootstrapped across RSET, which sets the output current into the load. With this configuration, circuit precision is maintained for load currents in the range from the reference's supply current (typically 30 A) to approximately 30 mA. The low dropout voltage of these devices maximizes the current source's output voltage compliance without excess headroom.
Two reference ICs are used, fed from a common unregulated input, VS. The outputs of the individual ICs are connected in series, as shown in Figure 25, which provide two output voltages, VOUT1 and VOUT2. VOUT1 is the terminal voltage of U1, while VOUT2 is the sum of this voltage and the terminal voltage of U2. U1 and U2 are chosen for the two voltages that supply the required outputs (see Output Table in Figure 25). If, for example, both U1 and U2 are REF192s, the two outputs are 2.5 V and 5.0 V.
Rev. I | Page 21 of 28
00371-026
VO (U1)
+ C4 1F
R1 3.9k
+VOUT1
VIN COMMON
D1 AD589
VO (D1)
+ C3 1F
+VOUT1 1.235V
REF19x Series
VIN
OUTPUT TABLE U1/U2 VC* VOUT (V) 5.0 3.3 4.5 5.0
2
REF195/ HI REF196 LO +VS = 6V
2
VIN
REF19x
3 SLEEP
REF194/ HI REF195 LO U1
VREF 6 GND
4
*CMOS LOGIC LEVELS
6
1F ISY ADJUST
R1 RSET P1 IOUT RL
VC
1
2
3
4
3
U3A U3B 74HC04 74HC04
(SEE TABLE) 4
REF19x
VIN IOUT x RL (MAX) + VSY (MIN) IOUT = VOUT RSET VOUT RSET + ISY (REF19x) >> ISY
+VOUT
2 3
00371-027
E.G., REF195: VOUT = 5V IOUT = 5mA R1 = 953 P1 = 100, 10-TURN
(SEE TABLE)
REF19x
4
U2
6
+ C2 1F
C1 0.1F VIN COMMON
Figure 27. A Low Dropout, Precision Current Source
VOUT COMMON
The governing equations for the circuit are
VIN = IOUT x RL ( Max ) + VSY (Min, REF 19x )
I OUT = VOUT + I SY (REF 19x ) RSET
Figure 28. Switched Output Reference
VOUT I SY (REF 19x ) RSET
SWITCHED OUTPUT 5 V/3.3 V REFERENCE
Applications often require digital control of reference voltages, selecting between one stable voltage and a second. With the sleep feature inherent to the REF19x series, switched output reference configurations are easily implemented with little additional hardware. The circuit in Figure 28 illustrates the general technique, which takes advantage of the output wire-OR capability of the REF19x device family. When off, a REF19x device is effectively an open circuit at the output node with respect to the power supply. When on, a REF19x device can source current up to its current rating, but sink only a few A (essentially, just the relatively low current of the internal output scaling divider). Consequently, when two devices are wired together at their common outputs, the output voltage is the same as the output voltage for the on device. The off state device draws a small standby current of 15 A (max), but otherwise does not interfere with operation of the on device, which can operate to its full current rating. Note that the two devices in the circuit conveniently share both input and output capacitors, and with CMOS logic drive, it is power efficient.
Using dissimilar REF19x series devices with this configuration allows logic selection between the U1/U2-specified terminal voltages. For example, with U1 (a REF195) and U2 (a REF196), as noted in the table in Figure 28, changing the CMOScompatible VC logic control voltage from HI to LO selects between a nominal output of 5 V and 3.3 V, and vice versa. Other REF19x family units can also be used for U1/U2, with similar operation in a logic sense, but with outputs as per the individual paired devices (see the table in Figure 28). Of course, the exact output voltage tolerance, drift, and overall quality of the reference voltage is consistent with the grade of individual U1 and U2 devices. Due to the nature of the wire-OR, one application caveat should be understood about this circuit. Since U1 and U2 can only source current effectively, negative going output voltage changes, which require the sinking of current, necessarily takes longer than positive going changes. In practice, this means that the circuit is quite fast when undergoing a transition from 3.3 V to 5 V, but the transition from 5 V to 3.3 V takes longer. Exactly how much longer is a function of the load resistance, RL, seen at the output and the typical 1 F value of C2. In general, a conservative transition time is approximately several milliseconds for load resistances in the range of 100 to 1 k. Note that for highest accuracy at the new output voltage, several time constants should be allowed (>7.6 time constants for <1/2 LSB error @ 10 bits, for example).
KELVIN CONNECTIONS
In many portable applications where the PC board cost and area go hand-in-hand, circuit interconnects are very often narrow. These narrow lines can cause large voltage drops if the voltage reference is required to provide load currents to various functions. The interconnections of a circuit can exhibit a typical line resistance of 0.45 m/square (1 oz. Cu, for example).
Rev. I | Page 22 of 28
00371-028
REF19x Series
In applications where these devices are configured as low dropout voltage regulators, these wiring voltage drops can become a large source of error. To circumvent this problem, force and sense connections can be made to the reference through the use of an operational amplifier, as shown in Figure 29. This method provides a means by which the effects of wiring resistance voltage drops can be eliminated. Load currents flowing through wiring resistance produce an I-R error (ILOAD x RWIRE) at the load. However, the Kelvin connection overcomes the problem by including the wiring resistance within the forcing loop of the op amp. Because the op amp senses the load voltage, op amp loop control forces the output to compensate for the wiring error and to produce the correct voltage at the load. Depending on the reference device chosen, operational amplifiers that can be used in this application are the OP295, OP292, and OP183.
VIN
2
The circuit in Figure 30 illustrates this concept, which borrows from the switched output idea of Figure 28, again using the REF19x device family output wire-OR capability. In this case, since a constant 5 V reference voltage is desired for all conditions, two REF195 devices are used for U1 and U2, with their on/off switching controlled by the presence or absence of the primary dc supply source, VS. VBAT is a 6 V battery backup source that supplies power to the load only when VS fails. For normal (VS present) power conditions, VBAT sees only the 15 A (maximum) standby current drain of U1 in its off state. In operation, it is assumed that for all conditions, either U1 or U2 is on, and a 5 V reference output is available. With this voltage constant, a scaled down version is applied to the Comparator IC U3, providing a fixed 0.5 V input to the negative input for all power conditions. The R1 to R2 divider provides a signal to the U3 positive input proportionally to VS, which switches U3 and U1/U2, dependent upon the absolute level of VS. In Figure 30, Op Amp U3 is configured as a comparator with hysteresis, which provides clean, noise-free output switching. This hysteresis is important to eliminate rapid switching at the threshold due to VS ripple. Furthermore, the device chosen is the AD820, a rail-to-rail output device. This device provides HI and LO output states within a few mV of VS, ground for accurate thresholds, and compatible drive for U2 for all VS conditions. R3 provides positive feedback for circuit hysteresis, changing the threshold at the positive input as a function of the output of U3.
VIN RLW
2 3 1
VIN SLEEP
3
+VOUT SENSE +VOUT FORCE
A1
RLW
VOUT 6
REF19x
GND
4
1F
RL
Figure 29. A Low Dropout, Kelvin-Connected Voltage Reference
FAIL-SAFE 5 V REFERENCE
Some critical applications require a reference voltage to be maintained at a constant voltage, even with a loss of primary power. The low standby power of the REF19x series and the switched output capability allow a fail-safe reference configuration to be implemented rather easily. This reference maintains a tight output voltage tolerance for either a primary power source (ac line derived) or a standby (battery derived) power source, automatically switching between the two as the power conditions change.
+VBAT +VS R1 1.1M R3 10M
3+ 2-
00371-029
A1 = 1/2 OP295 1/2 OP292 100k OP183
R6 100
C2 0.1F Q1 2N3904
2 3
(SEE TABLE)
REF195
4
U1
6
5.000V
7 6 4
C1 0.1F
AD820
3
U3
2
R2 100k
(SEE TABLE)
REF195
4
U2
6
+ C3 1F
R4 900k R5 100k
VOUT COMMON
Figure 30. A Fail-Safe 5 V Reference
Rev. I | Page 23 of 28
00371-030
VS, VBAT COMMON
C4 0.1F
REF19x Series
For VS levels lower than the lower threshold, U3 output is low; thus, U2 and Q1 are off while U1 is on. For VS levels higher than the upper threshold, the situation reverses, with U1 off and both U2 and Q1 on. In the interest of battery power conservation, all of the comparison switching circuitry is powered from VS and is arranged so that when VS fails, the default output comes from U1. For the R1 to R3 values, as shown in Figure 30, lower/upper VS switching thresholds are approximately 5.5 V and 6 V, respectively. These can be changed to suit other VS supplies, as can the REF19x devices used for U1 and U2, over a range of 2.5 V to5 V of output. U3 can operate down to a VS of 3.3 V, which is generally compatible with all REF19x family devices.
100
REF195
2 6 4
10F + 1F 57k 1%
10F
+
0.1F
3
0.1F
10k 1%
1/4 OP492
-
11
+
4 1
2N2222
2
500 0.1%
LOW POWER, STRAIN GAGE CIRCUIT
As shown in Figure 31, the REF19x family of references can be used in conjunction with low supply voltage operational amplifiers, such as the OP492 or the OP283, in a self-contained strain gage circuit in which the REF195 is used as the core. Other references can be easily accommodated by changing circuit element values. The references play a dual role, first as the voltage regulator to provide the supply voltage requirements of the strain gage and the operational amplifiers, and second as a precision voltage reference for the current source used to stimulate the bridge. A distinct feature of the circuit is that it can be remotely controlled on or off by digital means via the SLEEP pin.
10k 1% 0.01F 20k 1%
13
1/4 OP492
+ 10k 1%
-
14
20k 1%
6
12
2.21k
1/4 OP492
+
-
7
OUTPUT
5
9
10
+
Figure 31. A Low Power, Strain Gage Circuit
Rev. I | Page 24 of 28
00371-031
1/4 OP492
-
8
20k 1% 20k 1%
REF19x Series OUTLINE DIMENSIONS
0.400 (10.16) 0.365 (9.27) 0.355 (9.02)
8 1 5
4
0.280 (7.11) 0.250 (6.35) 0.240 (6.10)
5.00 (0.1968) 4.80 (0.1890)
0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) MAX 0.195 (4.95) 0.130 (3.30) 0.115 (2.92)
0.100 (2.54) BSC 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14)
4.00 (0.1574) 3.80 (0.1497)
8 1
5 4
6.20 (0.2440) 5.80 (0.2284)
0.015 (0.38) MIN SEATING PLANE 0.005 (0.13) MIN
0.015 (0.38) GAUGE PLANE 0.430 (10.92) MAX
0.014 (0.36) 0.010 (0.25) 0.008 (0.20)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) 0.25 (0.0099) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157)
45
0.51 (0.0201) 0.31 (0.0122)
Figure 32. 8-Lead Plastic Dual In-Line Package [PDIP] (N-8) P-Suffix Dimensions shown in inches and (millimeters)
3.10 3.00 2.90
Figure 34. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) S-Suffix Dimensions shown in millimeters and (inches)
8
5
4.50 4.40 4.30
1 4
6.40 BSC
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX SEATING 0.20 PLANE 0.09
8 0
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AA
Figure 33. 8-Lead Thin Shrink Small Outline Package [TSSOP] (RU-8) Dimensions shown in millimeters
Rev. I | Page 25 of 28
060506-A
COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
070606-A
REF19x Series
ORDERING GUIDE
Model REF191ES REF191ES-REEL REF191ESZ 1 REF191ESZ-REEL1 REF191GP REF191GPZ1 REF191GS REF191GS-REEL REF191GSZ1 REF191GSZ-REEL1 REF192ES REF192ES-REEL REF192ES-REEL7 REF192ESZ1 REF192ESZ-REEL1 REF192ESZ-REEL71 REF192FS REF192FS-REEL REF192FS-REEL7 REF192FSZ1 REF192FSZ-REEL1 REF192FSZ-REEL71 REF192GP REF192GPZ1 REF192GRU REF192GRU-REEL7 REF192GRUZ1 REF192GRUZ-REEL71 REF192GS REF192GS-REEL REF192GS-REEL7 REF192GSZ1 REF192GSZ-REEL1 REF192GSZ-REEL71 REF193GS REF193GS-REEL REF193GSZ1 REF193GSZ-REEL1 REF194ES REF194ES-REEL REF194ESZ1 REF194ESZ-REEL1 REF194FS REF194FSZ1 REF194GP REF194GPZ1 REF194GS REF194GS-REEL REF194GS-REEL7 REF194GSZ1 REF194GSZ-REEL1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead PDIP 8-Lead PDIP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead PDIP 8-Lead PDIP 8-Lead TSSOP 8-Lead TSSOP 8-Lead TSSOP 8-Lead TSSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead PDIP 8-Lead PDIP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N Package Option S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) P-Suffix (N-8) P-Suffix (N-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) P-Suffix (N-8) P-Suffix (N-8) RU-8 RU-8 RU-8 RU-8 S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) P-Suffix (N-8) P-Suffix (N-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) Minimum Quantities/Reel 2500 2500
2500 2500 2500 1000 2500 1000 2500 1000 2500 1000
1000 1000 2500 1000 2500 1000 2500 2500 2500 2500
2500 1000 2500
Rev. I | Page 26 of 28
REF19x Series
Model REF194GSZ-REEL71 REF195ES REF195ES-REEL REF195ESZ1 REF195ESZ-REEL1 REF195FS REF195FS-REEL REF195FSZ1 REF195FSZ-REEL1 REF195GP REF195GPZ1 REF195GRU REF195GRU-REEL7 REF195GRUZ1 REF195GRUZ-REEL71 REF195GS REF195GS-REEL REF195GS-REEL7 REF195GSZ1 REF195GSZ-REEL1 REF195GSZ-REEL71 REF196GRU-REEL7 REF196GRUZ-REEL71 REF196GS REF196GS-REEL REF196GSZ1 REF196GSZ-REEL1 REF196GSZ-REEL71 REF198ES REF198ES-REEL REF198ESZ1 REF198ESZ-REEL1 REF198ESZ-REEL71 REF198FS REF198FS-REEL REF198FSZ1 REF198FSZ-REEL1 REF198GP REF198GPZ1 REF198GRU REF198GRU-REEL7 REF198GRUZ1 REF198GRUZ-REEL71 REF198GS REF198GS-REEL REF198GSZ1 REF198GSZ-REEL1
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead PDIP 8-Lead PDIP 8-Lead TSSOP 8-Lead TSSOP 8-Lead TSSOP 8-Lead TSSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead TSSOP 8-Lead TSSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead PDIP 8-Lead PDIP 8-Lead TSSOP 8-Lead TSSOP 8-Lead TSSOP 8-Lead TSSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N
Package Option S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) P-Suffix (N-8) P-Suffix (N-8) RU-8 RU-8 RU-8 RU-8 S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) RU-8 RU-8 S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) P-Suffix (N-8) P-Suffix (N-8) RU-8 RU-8 RU-8 RU-8 S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8)
Minimum Quantities/Reel 1000 2500 2500 2500 2500
1000 1000 2500 1000 2500 1000 1000 1000 2500 2500 1000 2500 2500 1000 2500 2500
1000 2500 2500 2500
Z = Pb-free part.
Rev. I | Page 27 of 28
REF19x Series NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners C00371-0-10/06(I)
Rev. I | Page 28 of 28

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